CDD ingénieur FPGA/traitement du signal

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CDD ingénieur FPGA/traitement du signal

Message par kaiser » 01 août 2008 19:49

Date : 25 juillet 2008 11:17:08 HAEC
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Objet : [asr-forum] Offre CDD ingénieur FPGA/traitement du signal
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Dans le cadre de l'ANR TCHATER, un poste d'ingénieur de recherche est à pourvoir au LIP (ENS-Lyon).


Florent de Dinechin

Research engineer position available:
Implementation of a signal processing pipeline for 40Gb/s optical transmission on an FPGA-based board

Duration: 24 months, starting October 2008

Location: Projet Arénaire, LIP, École Normale Supérieure de Lyon, France

Salary: 2000 - 2300 euros net per month.

Useful technical skills:
Digital signal processing
FPGA programming
Experience with high-speed serial links on Altera Stratix
VHDL or Verilog language
Altera Quartus or Xilinx ISE development environement
English or French

The TCHATER project (Alcatel – E2V -- ENS-Lyon – ENST – IRISA) aims at demonstrating a coherent terminal operating at 40Gbit/s using efficient polarization division multiplexing. The terminal will benefit to next-generation high information-spectral density optical networks, while offering straightforward compatibility with current 10Gbit/s networks. Advanced high-speed analog-to-digital converters will be designed within the project. In addition, the prototype will use FPGAs for real-time signal processing.

The mission of the engineer will be to program these FPGAs, starting with algorithms developed and evaluated off-line by the project partners. As the FPGAs work at a much lower frequency than the transmitted signals, they will have to absorb and process several tens of samples at each cycle. The main challenges are the synchronization of data from many high-speed links, and making the best use of the FPGA resources to obtain the required computation throughput.

Contact: 04 72 72 85 03


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